Beschreibung
A global Electronics client of mine are currently looking for Mixed Signal Design Verification Engineer to join them ASAP on a contract basis, the work will be partly remote and partly on-site in Switzerland.
Main Requirements/Responsibilities:
- Behavioral model creation for analog blocks in System Verilog (SV) language
- Writing testbenches for model vs. schematic verification in SV with assertions for self-checking tests
- (strong) Experience with mixed-signal simulations in Virtuoso framework
- Analog background to understand a circuit from a schematic
- Electronics/Semiconductor background
- Excellent communication skills
Vacancy Summary:
Job Type: Contract
Duration: 3 months (Initial)
Location: Switzerland/Remote
Salary: Negotiable (DOE)
If you are interested in this role or know anyone who might be please forward your most up to date CV ASAP and I will be in touch to discuss further. Alternatively, you can give me a call to find out more.
*AS ALWAYS REFERRALS ARE MUCH APPRECIATED*
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