Digital Design Expert for FPGAs and ASICs - CEO semify GmbH
Graz, Österreich
Weltweit
Electronics
Graz, Österreich
Weltweit
Electronics
Profilanlagen
CV - Klaus Strohmayer
Skills
ARM ArchitekturAtlassian JiraBoolesche AlgebraBugzillaC++Rational ClearcaseComputerprogrammierungInformation EngineeringDatenmanagementDebuggingDigitale ElektronikLogiksynthesePerlFPGAGitHubSCADATrouble-TicketPythonMATLABPerforceCadence VirtuosoRiscSimulinkSoftwareentwicklungSubversionSystemverilogTool Command LanguageVerilogVhdlVivadoScriptingPicmicroAsicCypressGitLabGitCshell
Cortex, ARM Cortex, ASIC Design, ASIC, digital logic, Bugzilla, C/C++, Cadence, Programming, C-shell, Cypress, Data Management, Digital Electronics, FPGA, Git, GitHub, GitLab, ClearCase, Information Engineering, digital development, Issue Tracking, JIRA, Digital Design, Matlab, Excel, Office, PowerPoint, Word, Microcontroller, Perforce, Perl, Python, Scripting, Simulink, debugging, development cycle, SVN, ICs, SystemVerilog, TCL, VHDL, Verilog, Vivado,
Digital Design, RISC-V, SystemVerilog
Erfahrung
Berufserfahrungmehr als 10 Jahre
Freelancer seit2020
Sprachen
DeutschMutterspracheEnglischverhandlungssicher
Projekthistorie
Digital Design for automotive microcontroller systems
Automobil und Fahrzeugbau
>10.000 Mitarbeiter
Definition and implementation of digital modules for an ASIL D microcontroller sub system. The implementation is done using SystemVerilog.
Architecture of a microcontroller (RISC-V) based waveform generator implemented in an FPGA.
semify GmbH
Telekommunikation
< 10 Mitarbeiter
Supporting a wide range of interfaces (SPI, I2C, UART,...)
Using Xilinx Atrix FPGA
Digital concept and architecture of a I3C hub device
Telekommunikation
500-1000 Mitarbeiter
Provided detailed specification of digital subblocks and effort estimations. Carried out digital design reviews of the sub blocks
Architecture and digital implementation of Cortex M33 microcontroller system
Telekommunikation
500-1000 Mitarbeiter
Performed RTL implemented several key block (eg. FLASH controller)
Bringing the whole system onto an FPGA for prototyping and early FW development
Full digital design for a audio power amplifier including digital signal processing and I2C interface
Telekommunikation
10-50 Mitarbeiter
Performed digital design (SystemVerilog), Synthesis, DfT and Gatelevel simulation. Supported AMS toplevel simulation
Integration of several IP blocks for an graphics IP providing AXI and AHB interfaces.
Automobil und Fahrzeugbau
>10.000 Mitarbeiter
Implementation of the decompression algorithm for graphics applications.
Perfomred CDC and RDC of muli million gate IP
Group Manager
NXP Semiconductor
Ramping of a Digital Design Team from two to eight
team members. Responsible for the digital
development of a Contactless Interface IP based on
an UVM testbench within a multi-cultural and multisite
team.
Team Lead / Group Manager
Dialog Semiconductors
Responsible for ramping, managing and developing the digital design team in Graz (13
people). Organize and drive group internal and external digital design and verification
reviews including Linting and CDC analysis.
Developing of design and verification strategies for Power-Management ICs and
spreading them within the company. Driving the development of ADC specific generic
bus system.
Digital Design and Group Manager
Dialog Semiconductors
Started as a Digital Design Engineer and covered
various digital design and verification related
functions. Taken over the role as a Group manager
for the digital design team in Graz.
...
Teaching
Digital designer
Infineon Technologies
within Infineon Technologies in Villach and Graz. The work comprised the whole ASIC
development cycle, from concept and specification over implementation and
verification until evaluation.
Using FPGAs for concept evaluation was also part of my work.
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