07.08.2025 aktualisiert
100 % verfügbar
Expert Firmware Engineer, Embedded Firmware Architect, Complex SoC HW/FW Co-design expert
München, Deutschland
Weltweit
Bachelor of Engineering in Electronics & CommunicationsSkills
VDSLAsymmetric Digital Subscriber LineTelekommunikationComputerprogrammierungContinuous IntegrationDevOpsDigital Subscriber LineEmbedded C++Embedded SystemsEmbedded SoftwareFirmwareFPGAScrumEchtzeit-BetriebssystemeVerilog
Embedded Firmware Development
Extensive expertise in embedded C & assembly level programming for real-time systems, with specialized knowledge in developing firmware for complex broadband communication SoCs.
Digital Signal Processing
Advanced skills in DSP implementation, including Layer-1/2/3 data path processing, and protocol processing for communication systems.
Hardware-Software Co-design
Comprehensive experience in HW-SW/FW co-design & emulation, with proficiency in developing end-to-end firmware solutions for mission-critical systems.
RTOS & Bare-metal Systems
Proficiency with ThreadX and other real-time operating systems, implementing real-time scheduling for embedded applications.
FPGA Development
Experience with Verilog and FPGA development for high-performance embedded systems.
Modern Development Practices
Knowledge of CI/CD, Agile/Scrum, and DevOps methodologies using Git and Jenkins for embedded firmware development.
Broadband Communication Systems
Specialized knowledge in DSL, VDSL, ADSL technologies, PON technology and high speed data center interconnect DSPs.
Extensive expertise in embedded C & assembly level programming for real-time systems, with specialized knowledge in developing firmware for complex broadband communication SoCs.
Digital Signal Processing
Advanced skills in DSP implementation, including Layer-1/2/3 data path processing, and protocol processing for communication systems.
Hardware-Software Co-design
Comprehensive experience in HW-SW/FW co-design & emulation, with proficiency in developing end-to-end firmware solutions for mission-critical systems.
RTOS & Bare-metal Systems
Proficiency with ThreadX and other real-time operating systems, implementing real-time scheduling for embedded applications.
FPGA Development
Experience with Verilog and FPGA development for high-performance embedded systems.
Modern Development Practices
Knowledge of CI/CD, Agile/Scrum, and DevOps methodologies using Git and Jenkins for embedded firmware development.
Broadband Communication Systems
Specialized knowledge in DSL, VDSL, ADSL technologies, PON technology and high speed data center interconnect DSPs.
Erfahrung
Berufserfahrungmehr als 10 Jahre
Freelancer seit2025
Sprachen
Englischverhandlungssicher
Projekthistorie
- Architected, designed, developed and brought-up end-to-end firmware for ITU-T G.Fast (G.9701) multimode DSL residential gateway (VRX 619) on proprietary complex SOC.
- Bring-up firmware state machine (Training, Showtime) on Virtual Platform for simulation &
Palladium emulator for pre-silicon validation. - Developed and fine-tuned Layer-1 (PHY) algorithms: SNR estimation, bit-loading, dynamic
bandwidth allocation, data rate adaptation, loss-of-signal detection, PLL improvements. - Architected, designed, and developed, Layer-2 data path firmware processing on proprietary
protocol processor using assembly level programming. - Contributed to 800 Gbps PAM4 data-center interconnect DSP (KeyStone) firmware.
- Led exceptional efforts in system stability tasks, task forces, interoperability topics,
performance fine-tuning, and root-causing HW-IP weaknesses and efficient firmware
solutions.
- Engineered Layer-2 and Layer-1 firmware solutions for custom SOCs designed for multiport
(8, 16, 32, 48, 64) DSL (VDSL and ADSL) line-card solutions intended for Central Office
deployments. - Designed and implemented robust data path processing including ATM, AAL5, EFM-TC
covering packet encapsulation, decapsulation, ATM cell delineation, EFM sync
detection, packet fragmentation/reassembly and rate throttling. - Design and development of Layer-2 Retransmission mechanism based on G.Inp
(G.998.4) standard to mitigate impulse noise. - Developed key features for G.Vector (G.993.5) to mitigate crosstalk interference on
VDSL2 connections, including Fast-LOS detector to accelerate link tear-down and
retrain, Fast Retransmission Return Channel (RRC) scheme to mitigate the symbol
delay topics in RRC processing. - Led efforts in system stabilization topics and debugging aspects across both physical
layer and Layer-2 covering both VDSL and massive vectoring systems.
- Led embedded firmware development activities for various processing blocks of network processor functionality (Layer-3 – data path processing) on custom Network Processor SOCs, integrating multiple hardware IP cores and multi-core packet processing units using assembly language programming.
- Engineered, and developed various critical firmware modules in assembly such as
- Layer-2 and Layer-3 switching for protocols like Ethernet, IP, IPoA, PPPoA, PPPoE, VLAN cross connect.
- Traffic Policing flows with high timing resolution.
- MAC address translation, access control.
- Control packet classification and forwarding to control plane based on HW lookup.
- Deep packet inspection for protocol identification and flow classification.
- Learning/aging, packet editing, multicast and broadcast handling using HW & FW.
- QOS and hierarchical queue scheduling and WRED mechanisms.