26.06.2026 aktualisiert
100 % verfügbar
analog Designer, FPGA design
Reutlingen, Deutschland
Deutschland +5
Dipl. Ing. Elektrotchnikinfo: Deutschland, Österreich, Schweiz, Italien, Frankreich, Polen
Skills
FPGAPythonVerilogVhdl
analog Design
CADENCE virtuoso
spectre, ams
wreal
behavioral modelling
Delta Sigma ADC
LDO
ADC
DAC
PLL
______________________________
FPGA design
requirements engineering
Vivado
Vitis
microBlaze
axi
HLS
Verilog , VHDL
digitaler Zwilling, digitale Modelle von 3rd party ICs , Sensoren und Aktuatoren
I2C
I3C
SPI
______________
Matlab, Simulink, python
Erfahrung
Berufserfahrung5 - 10 Jahre
Freelancer seit2020
Sprachen
DeutschMutterspracheEnglischverhandlungssicher
Projekthistorie
Development of Xilinx FPGA-based measurement systems
for highly parallelized data acquisition systems
- FPGA design in Vivado
- languages: VERILOG and VHDL
- advising and supervising junior technician for PCB
schematic entry and PCB layout
- writing digital models for 3rd party (anlaog) ICs and
actuators and sensors for full system simulation ( FPGA+
microBlaze+software + 3rd party hardware)
- writing firmware for 1st and 2nd generation of measurement
platfom in C++ running on ARM uC (1st gen) or Microblaze
uC(2nd gen)
- putting FPGA based system into service incl. debug
analogue design of super low power Delta Sigma ADC for
infrared detector read-out IC (column ADC for 640x512
array) including decimation filter employing dynamic flipflops
0.35um CMOS
project management and sub-system design: MEMS
oscillator with temperature compensation employing fractional
PLL, project management and system design
designing programmable ALU executing temperature
compensation model using self-written "assembler" code
0.14um CMOS technology