29.10.2026 aktualisiert
100 % verfügbar
Microelectronic Engineer (FPGA/ASIC Design & Verif)
Stuttgart, Deutschland
Deutschland
Electric and Microelectronic EngineerSkills
FPGAMikroelektronikSystemcVerilogAsicVHDL-Programmierung
- SoC design and verification, methodologies & tools
- writing verification plans and test plans
- RTL coding (VHDL, Verilog, SystemVerilog)
- Low-power verification (UPF)
- DFT concepts and associated tests
- Testbench development (UVM, SystemVerilog, C testcases)
- Scripting skills: Python, C, Tcl, Shell
- Complex SoC architectures:
* ARM systems, cache coherency, SMMU, interconnects,
* PCIe, Ethernet, DDR controllers, trace & debug, interrupts
- SoC bus protocols and interfaces:
* AMBA ( AXI / AHB / APB / ACE / CHI, …),
* Standard peripherals (SPI, eMMC, JTAG, UART, …)
- Memory interfaces (DDR4/5, LPDDR5)
- Notions of Formal Verification
- Notions of HLS (SystemC TLM, Matlab) for Modeling & Verification
Erfahrung
Berufserfahrungmehr als 10 Jahre
Freelancer seit2022
Sprachen
DeutschverhandlungssicherEnglischgutFranzösischgut
Projekthistorie
Senior Microelectronic Engineer
* FPGA and Structured ASIC design prototyping ;
* ASIC Frontend Activities and Post-Fab Testing;
* RTL and Functional Verification;
* Digital/Analog Co-simulation;
* Microcontrollers programming;
* Prepare technical specification, test & validation plan;
* PCB Heat sink and thermal consideration;
* Analogic & digital Signal processing;
* Functional Test, Debug, signal's analyzing (Logic Analyser, oscilloscope...);
* Knowledge and implementation of the EMC-relevant standards;
* Knowledge in Circuit diagram, schematic, development and layout of industrial
electronics;
* Knowledge in mixed signal hardware development, Safety, PCB Design, simulation,
review, test & reparation
* Product Specification & certification.
Used methods und tools:
FPGA, Altera Hardcopy, Atmel CAP9H, Modelsim, PlanAhead, ISE, Modelsim, Xilinx ISE,
Planahead & Vivado, Altera Quartus, Hardware acceleration, STM32 uC, PCIe, GigaETH,
VHDL, Verilog, C/C++, TCL/TK , Batch, MS.Net, Eclipse, PIC, signal processing, Power
Electronic, Optoelectronic, Sensors, X-ray image processing, Motor Control et Regulations,
Mentor DxDesigner PCB & Hyperlynx DRC, Spice, Aldec Alint, SIL2, IEC 61131(IEC 62061),
IEC 61508.
* FPGA and Structured ASIC design prototyping ;
* ASIC Frontend Activities and Post-Fab Testing;
* RTL and Functional Verification;
* Digital/Analog Co-simulation;
* Microcontrollers programming;
* Prepare technical specification, test & validation plan;
* PCB Heat sink and thermal consideration;
* Analogic & digital Signal processing;
* Functional Test, Debug, signal's analyzing (Logic Analyser, oscilloscope...);
* Knowledge and implementation of the EMC-relevant standards;
* Knowledge in Circuit diagram, schematic, development and layout of industrial
electronics;
* Knowledge in mixed signal hardware development, Safety, PCB Design, simulation,
review, test & reparation
* Product Specification & certification.
Used methods und tools:
FPGA, Altera Hardcopy, Atmel CAP9H, Modelsim, PlanAhead, ISE, Modelsim, Xilinx ISE,
Planahead & Vivado, Altera Quartus, Hardware acceleration, STM32 uC, PCIe, GigaETH,
VHDL, Verilog, C/C++, TCL/TK , Batch, MS.Net, Eclipse, PIC, signal processing, Power
Electronic, Optoelectronic, Sensors, X-ray image processing, Motor Control et Regulations,
Mentor DxDesigner PCB & Hyperlynx DRC, Spice, Aldec Alint, SIL2, IEC 61131(IEC 62061),
IEC 61508.
FPGA/ASIC/SoC Engineer with extensive experience leading the end-to-end development of complex,
high-performance hardware solutions for mission-critical aerospace, defense, medical, and industrial
applications. Specialized in FPGA architecture, multi-clock-domain VHDL RTL design, high-speed video
and signal-processing pipelines, and multi-gigabit serial interfaces. Proven expertise across the
complete FPGA development lifecycle, including verification, code coverage, CI/CD automation,
synthesis, place and route, static timing analysis, timing closure, hardware bring-up,
and system integration. Strong technical leadership skills, with experience translating
system-level requirements into scalable hardware architectures, coordinating engineering
activities, mentoring junior engineers, and collaborating across hardware, software,
and systems teams to deliver reliable, production-ready solutions.