Beschreibung
ASIC Digital Design Engineer - IC, ASIC, Verilog, Hardware, RTL experience required for an 8 month contract in Zurich, Switzerland.
My client, an international engineering company located in Zurich is looking for three (3) digital design engineers to start a brand new project for one of their customers (B2B). Sucessful applicants will be doing design and verification activities to include RTL design in Verilog or SystemVerilog, utilising the cadence tools suite (Incisive simulator).
The ideal candidate will have 5 years on the job experience as a digital design engineer and will be educated to Masters degree level (MSc etc.) or equivalent vocational qualification. Experience is required in RTL Design using Verilog or SystemVerilog and a basic knowledge surrounding UVM. English or German fluency is required, both would be beneficial.
This is an excellent opportunity to work on a brand new project and create a product in a lively, flexible team for a big name in the engineering world.