Beschreibung
Digital Design Engineer - Verilog, Cadence, RTL
Digital Design Engineer - Verilog, Cadence, RTL experience is required for a 1-2 month contract in Zurich
My client, an international engineering company located in Zurich is looking for a Digital design and verification engineer (Verilog expert) for a 6-8 month contract to complete a customer requirement.
The ideal candidate has at least 5 years of experience in Verilog coding and RTL design, experience of synthesising Verilog into ASIC is a plus.
English OR German language is mandatory.