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Senior ASIC Design Engineer, with Experiences thru the whole Design Flow, from Digital Entry - (System-)Verilog + VHDL - to DSM Backend and back.
FPGA knowledge for Xilinx, Altera, Lattice and MicroSemi. Inventor and Patentee for a FPGA structure.
Open Source Evangelist, always interested in challenging FPGA and migration projects.
Specialties: System-Verilog, VHDL. FPGAs. CVS, subversion, git, Makefiles. Release Management. Cell libraries, Reverse Engineering.
FPGA knowledge for Xilinx, Altera, Lattice and MicroSemi. Inventor and Patentee for a FPGA structure.
Open Source Evangelist, always interested in challenging FPGA and migration projects.
Specialties: System-Verilog, VHDL. FPGAs. CVS, subversion, git, Makefiles. Release Management. Cell libraries, Reverse Engineering.
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