FPGA Developer

My Master thesis also hardware implementation. My Master thesis title was "Hardware implementation of Basic Components for Posit Arithmetic." Posit is one of the techniques to represent numbers on hardware. Posit is a strong candidate for the next generation number format and it will be the replacement of the IEEE-754 format. In my thesis, I have developed RTL code for posit adder, multiplier and dot product. I also have a design data path and FSM for the RTL implementation. I have also synthesized the RTL code. In addition, to verify the correct functionality, I have compared the RTL results with Matlab results. As far as I know, I am the only person in the world who implemented Posit numbers on hardware. In that thesis, I have used programming language VHDL and Matlab. I have used hardware tools Xilinx, Vivado, ISE, Questa Sim and Model Sim.

My Master project also hardware implementation. My Master project title was '' Register Transfer Level Implementation of Massive MIMO Baseband Signal Processing''. In that project, I have solved the backward substitution technique for channel matrix. In that project, I have the design data path and FSM for RTL code and also synthesize the RTL code. The correct functionality was done by comparing the RTL results with Matlab results. In that project, I have used programming language VHDL and Matlab. I have used hardware tools Xilinx, Vivado, ISE, QuestaSim and ModelSim.