R&D FPGA design Engineer
Intel IDC
Skills
PCIE GEN3, USB3.0, LB60x, AXI, FPGA, Embedded Linux, Algorithm, Ethernet, FPGA synthesis-automation scripting environment, Python, TCL, ASIC, OVM, Firmware, PCB, VHDL, System Verilog, Xilinx/Altera/Lattice CPLD/FPGA, Lattice EPC2M FPGA, Altera, TDM, ATM, Ethernet and Mobile systems, CPLD, PowerPC, microprocessors, PCI, VHDL/System Verilog design and verification Constraints Writing, Timing, Closer, C, C++ programming
Projekthistorie
06/2012
-
05/2017
Working in company focused on global growth areas of processors, platforms, software and services
as a part of CPU chip design team
R&D FPGA design Engineer
Leading the development of Intel® Camera's IPU FPGA prototyping
- Overseeing the meticulous definition and review of design constraints to achieve timing closure on a
high speed multiple asynchronous clock domains design
- Responsible for the partition of the ASIC design into 2 Xilinx Virtex7 FPGA boards
- Designed additional Xilinx Spartan6 systems for the Camera's testing boards
- Successfully registering a reduction in debug count as well as increasing QOR via the integration of the
FPGA design into the ASIC's UVM/OVM verification environment
- Writing the FPGA synthesis-automation scripting environment in Python and TCL
- Extensive hands-on in-lab testing using Debug Tools and electronic test instruments (oscilloscope etc.)
- Performing a wide range of technical duties on a regular basis, from writing documentations and user
manuals for both HW and SW to coordinating effectively with Firmware, PCB and System teams
- Synthesis ASIC oriented VHDL and System Verilog Code of prototyped IP for Virtual Platform emulation
system with Synopsis ZEBU Tools
as a part of CPU chip design team
R&D FPGA design Engineer
Leading the development of Intel® Camera's IPU FPGA prototyping
- Overseeing the meticulous definition and review of design constraints to achieve timing closure on a
high speed multiple asynchronous clock domains design
- Responsible for the partition of the ASIC design into 2 Xilinx Virtex7 FPGA boards
- Designed additional Xilinx Spartan6 systems for the Camera's testing boards
- Successfully registering a reduction in debug count as well as increasing QOR via the integration of the
FPGA design into the ASIC's UVM/OVM verification environment
- Writing the FPGA synthesis-automation scripting environment in Python and TCL
- Extensive hands-on in-lab testing using Debug Tools and electronic test instruments (oscilloscope etc.)
- Performing a wide range of technical duties on a regular basis, from writing documentations and user
manuals for both HW and SW to coordinating effectively with Firmware, PCB and System teams
- Synthesis ASIC oriented VHDL and System Verilog Code of prototyped IP for Virtual Platform emulation
system with Synopsis ZEBU Tools
04/2009
-
05/2012
R&D FPGA design Engineer
Celtro Ltd Petah
Working in the company provides solutions and equipment in the cellular optimization for Mobile systems.
R&D FPGA design Engineer
FPGA design for Cellular systems with Xilinx/Altera/Lattice CPLD/FPGA (code is written in VHDL) and
advanced CPU applications based PQ and DDR3.
- Leading the development of FPGA based TDM Switch solution for Cellular Compassion System
- - Part of the Architecture development and Spec Definition
- - Responsible for the implementation of the design into Lattice EPC2M FPGA
- - Designed additional Altera Cyclone 4 blocks for the System Controller boards
- - Writing complex Test Bench based verification environments for functional verification and bug
reduction
- - Writing the FPGA synthesis-automation scripting environment in Python and TCL
- Extensive hands-on in-lab testing using Altera Signal TAP and electronic test instruments (oscilloscope
etc.)
R&D FPGA design Engineer
FPGA design for Cellular systems with Xilinx/Altera/Lattice CPLD/FPGA (code is written in VHDL) and
advanced CPU applications based PQ and DDR3.
- Leading the development of FPGA based TDM Switch solution for Cellular Compassion System
- - Part of the Architecture development and Spec Definition
- - Responsible for the implementation of the design into Lattice EPC2M FPGA
- - Designed additional Altera Cyclone 4 blocks for the System Controller boards
- - Writing complex Test Bench based verification environments for functional verification and bug
reduction
- - Writing the FPGA synthesis-automation scripting environment in Python and TCL
- Extensive hands-on in-lab testing using Altera Signal TAP and electronic test instruments (oscilloscope
etc.)
05/2006
-
03/2009
R&D HW Engineer
Nokia Siemens Networks Hod Ha Sharon
Working in the company provides solutions and equipment in the networking field for TDM, ATM, Ethernet
and Mobile systems.
R&D HW Engineer
-Board and FPGA design for Telecom technologies with Xilinx/Altera/Lattice CPLD/FPGA (code is written in
VHDL) and advanced CPU applications based PQ3 and DDR2
and Mobile systems.
R&D HW Engineer
-Board and FPGA design for Telecom technologies with Xilinx/Altera/Lattice CPLD/FPGA (code is written in
VHDL) and advanced CPU applications based PQ3 and DDR2
04/2003
-
05/2006
R&D HW Engineer
Freescale Semiconductor Herzelia
Working in the company developing the Communications Processors and evaluation boards in the
networking field
R&D HW Engineer
Board and FPGA design for Telecom technologies with Xilinx/Altera/Lattice CPLD/FPGA (code is written in
VHDL) and advanced CPU applications based PQ processors
networking field
R&D HW Engineer
Board and FPGA design for Telecom technologies with Xilinx/Altera/Lattice CPLD/FPGA (code is written in
VHDL) and advanced CPU applications based PQ processors
Reisebereitschaft
Verfügbar in den Ländern
Deutschland
